High-density-interconnect (hereinafter: HDI) multilayer circuits are an extremely large and fast-growing segment of the printed circuit board industry. In most of these HDI multilayer circuits, high circuit density is only required in the outermost layers. Conventional processes to form HDI circuit layers are sequential—connections between layers are formed from the outer layer to the inner layer. The fine features required and the typically “outside-in” methodology for layer-to-layer connection necessitates an extensive list of precision and often expensive process steps for each layer. The chemical baths needed to electroless plate copper into the layer-to-layer interconnections (hereinafter referred to as vias) are particularly expensive to install, operate and maintain. Therefore, to conserve cost, a relatively low-circuit-density multilayer circuit “core” is fabricated by conventional, relatively low-cost, methods, and HDI layers are added to either side as required. Typically, the low-circuit-density core consists of etched copper circuits separated by polymer laminate sheets and interconnected by copper-plated through-holes.
Conventional, prior art methods for manufacture of the HDI circuit layers are generally sequential processes. Most typically, copper foil and polymer dielectric are laminated to both sides of a low-circuit-density core. Formation of the electrical interconnections between the outer- and immediately underlying inner-layer follows, and then the definition of the outer-layer circuit pattern is undertaken. Most commonly, the pattern of via holes is formed in the copper foil by a common photolithography-etching method. Once the polymer dielectric is exposed in the areas of the via holes, the polymer dielectric is laser ablated down to the underlying copper pad on the outermost layer of the low-circuit-density core. The via holes thus formed are electroless and electrolytically plated and the pattern of the surface circuitry is etched by depositing and photolithographically defining a photopolymer mask and chemically etching away the exposed copper foil. Any additional HDI circuit layers are produced similarly, in a sequential process scheme.
This conventional methodology for producing HDI multilayer circuits suffers from several limitations. The plating operations are slow, expensive and require complicated chemistry. The via connections thus created have a residual ‘dimple’ that can distort overlying circuitry and entrap contaminants. Because the vias are not typically solidly filled, they cannot be vertically stacked to create interconnection across several layers without additional filling operations. Also due to uneven topography, the vias cannot generally be located in component attachment pads without additional filling operations because the connection of the component may be compromised. Even when filled, the dimples are a common source of failure due to evolution of entrapped volatiles or water during secondary processing operations. Further, the connection between the barrel of the via and the over- and underlying-circuitry is located at points of high mechanical stress due to coefficient of thermal expansion mismatch with the polymer dielectric. Finally, the sequential nature of the process is slow and a defect in late stages of processing creates substantial losses in the near-finished assembly.
The deficiencies of current methods for manufacture of HDI multilayer circuits can thus be summarized as follows:                current methods rely on sequential processing, which is susceptible to cumulative yield loss, whereas parallel processing of HDI circuit layers, in contrast, would provide the opportunity to verify and use only “known good layers”;        vias used to electrically interconnect layers are formed from the outside-in, which creates defects in the outside layer of circuitry;        via creation is also a sequential process that cannot be undertaken until the materials for the next HDI layer have been laminated to the core;        conventional electroless and electrolytic methods to plate the vias are slow, complex and expensive;        plated vias suffer from concentrated areas of mechanical stress that are susceptible to failure; and        the residual dimple in plated vias can entrap contaminants, distort outer layers, inhibit the creation of via stacks, and can interfere with secure component attachment when the via is located in the pad.        
Some prior art methods have sought to overcome these deficiencies. For example, the methods of Gallagher et al, U.S. Pat. No. 5,948,533, teach the use of layers of conductive-compound-filled vias in patterned polymer dielectric materials (hereinafter: via layers) to connect circuit layers. The use of such methods enables a parallel-fabricated via layer and copper sheet to be laminated to either side of a conventionally processed core. This eliminates the deficiencies of sequentially produced vias, copper plating of vias and surface layer defects. Additional layers must still, however be added sequentially. In an alternative embodiment, via layers can be used to interconnect and conjoin a core and a multiplicity of parallel-fabricated two-sided HDI circuits with plated through-connections in a single lamination. While this method provides a means to parallel-fabricate all circuit and via layers, the via connections between the two sides of the two-sided circuits must still be plated.
Several other prior art methods employ similar strategies, but with variations in the material used as the electrically conductive compound (e.g. Tsukamoto, U.S. Pat. No. 6,281,448; Haas et al, U.S. Pat. No. 6,673,190).
While these publications describe substantial improvements in the art, these prior art methods do not completely remedy the deficiencies of sequential processing (when single-sided or adhesive sheet plus foil strategies are employed) or plated vias (when two-sided HDI circuits are employed).